No image available
No image available
No image available
No image available
No image available
No image available
No image available
No image available
· 2020
No image available
No image available
· 1994
In exceeding the limits of the size-speed envelope during the design of a GaAs digitizer chip, a new clock speed limitation of stochastic nature was identified. Its importance stems from the fact, discovered during the simulation of the digitizer, that the stochastic components of delays do not affect the performance of the chip in the same manner as the delays themselves. Once discovered and understood, the effect is easily demonstrated even on very small circuits. A functionally correct digital design, based on the assumption that the propagation delays are larger than actual, so as to subsume fluctuations, may not work correctly at any clock speed. This discovery justifies the introduction of a new chapter of logic design, referred to as "stochastic", currently relevant only in applications requiring performance beyond the state of the art defined by the commercial imperative of high production yield. Scientific instrumentation, like DUMAND II, is such an application. The stochastic limitation stems from two sources: a probability distribution of signal transition delays within individual logic cells because of circuit parameter fluctuations over the surface of the chip, and a probability distribution of signal propagation delays between cells caused by fluctuations in routing lengths. The former can affect even small chips if they are sufficiently fast, while the latter might be the dominant stochastic limitation on over-all speed in chips with large clock distribution trees. Such a situation exists within the digitizer, where a very large distribution network delivers the master clock signal to thousands of leaves which must be synchronized, but are actually out of phase as a consequence of position-related fluctuations in propagation delays. A second contribution to VLSI design, also stemming from work on the digitizer, is a power reduction through capacitance cancellation in the different part of current steering logic cells. As much as a thirty percent power reduction can be obtained without affecting the signal to noise ratio and the transition speed.