A detailed analysis based on simulation results is presented, focusing on two key architectural factors -- the fine-grain synchronization capacity and the scheduling mechanism for enabling instructions. On one hand, our results provide experimental evidence that software pipelining is an effective method for exploiting fine-grain parallelism in loops. On the other, the experiments have also revealed the (somewhat pessimistic) fact that even a fully software pipelined code may not achieve good performance if the overhead for fine-grain synchronization exceeds the capacity of the machine."

"This thesis describes a compile-time loop scheduling scheme and a supplementary storage reduction scheme to generate code for computer architectures which exploit fine-grain parallelism, such as superscalar, VLIW, and superpipeline machines." --